Conference Programme

	THURSDAY MORNING, March 20, 2003 – PALAZZO ANTONINI
8.00 – 8.40	Registration in Palazzo Antonini
8.40 – 9.00	Conference Opening and Welcome address
9.00	Session 1.1: Transistor architecture and fabrication Chairpersons: K. De Meyer (IMEC, Leuven, Belgium) and S. Cristoloveanu (IMEP, Grenoble, France)
9.00 – 9.40	Invited paper: CMOS Downsizing toward sub-10nm H. Iwai, Tokyo Institute of Technology, Tokyo, Japan
9.40 – 10.00	Towards the limits of conventional MOSFETs G. Bertrand (1,2), S. Deleonibus (1), B. Previtali (1), G. Guegan (1), X. Jehl (1), M. Sanquer (1), F. Balestra (2); 1) CEA-LETI, Grenoble, France; 2) Institut de Microélectronique, d’Electromagnétisme et de Photonique (IMEP), Grenoble, France
10.00 – 10.20	Nanoscale SOI-MOSFETs with Non-Planar Multiple Gates M. Lemme (1), T. Mollenhauer (1), W. Henschel (1), T. Wahlbrink (1), H. Kurz (1), M. Baus (2), B. Spangenberg (2); 1) Advanced Microelectronic Center Aachen (AMICA), Aachen, Germany; 2) Institüt für Halbleitertechnik, Aachen, Germany
10.20 – 10.40	Impact of carbon on short channel behaviour in deep submicronic silicon N MOSFETs K. Romanjek (1), G. Ghibaudo (1), T. Ernst (2); 1) IMEP, UMR, CNRS, Grenoble, France; 2) CEA-LETI, Grenoble, France
10.40 - 11.00	Coffee Break and Poster Session
11.00 – 11.20	Impact of Doping Concentration Gradient and Spacer Thickness on Device Performance of UTB-SOI CMOS T. Schulz, C. Pacha, R.J. Luyken, M. Städele, J. Hartwich, L. Dreeskonrnfeld, E. Landgraf, J. Kretz, W. Rösner, M. Specht, F. Hoffmann and L. Risch; Infineon Technologies AG, Munich, Germany
11.20 – 11.40	Channels Separation in FINFETs F. Daugé (1), J. Pretet (1,3), A. Vandooren (2), L. Mathew (2), B.-Y. Nguyen (2), J. Jomaah (1), S. Cristoloveanu (1); 1) IMEP (UMR CNRS/INPG/UJF), Grenoble, France; 2) Motorola, Digital DNA Lab., Austin, TX, USA; 3) ST-Microelectronics, Crolles, France
11.40 – 12.00	On the Role of Corner Effect in FINFETs A. Burenkov, J. Lorenz; Fraunhofer Institute of Integrated Systems and Device Technology, Erlangen, Germany
12.00 – 12.20	Unified Analitical Model of Threshold Voltage in Symmetric and Asymmetric Double-Gate MOSFETs D. Munteanu (1), J.L. Autran (1), S. Harrison (1,2), T. Skotnicki (2); 1) L2MP, Marseille, France ; 2) ST-Microelectronics, Crolles, France
	THURSDAY AFTERNOON, March 20, 2003 – PALAZZO ANTONINI
14.20	Session 1.2: Capacitance and Gate current in advanced devices Chairpersons: S. Deleonibus (CAE-LETI Grenoble, France) and Y. Ponomarev (Philips Research, Leuven, Belgium)
14.20 – 14.40	Reduction of parasitic capacitance in vertical MOSFET’s by fillet local oxidation (FILOX) C.H. de Groot (1), V.D. Kunz (1), T. Uchino (1), P. Ashburn (1), D.C. Donaghy (2), S. Hall (2), Y. Wang (3), P.L.F. Hemment (3); 1) Dep. Of Electronics & Computer Science, University of Southampton, Southampton, UK; 2) Dep. Of Electrical Engineering and Electronics, University of Liverpool, Liverpool, UK; 3) School of Electronics, Computing & Maths, University of Surrey, Guildford, UK
14.40 – 15.00	Investigation of Floating Body Effects on SOI MOSFET Gate Tunneling Currents M. Bawedin (1), M. Estrada (2), D. Flandre (1); 1) Microelectronics Laboratory, Université catholique de Louvain, Louvain-la-Neuve, Belgium; 2) Departemento de Ingeniería Eléctrica, Seccíon de Electrónica del Estado Sólido, CINVESTA V, Mexico
15.00 – 15.20	Modeling the Inversion Electron Tunneling Currents through Ultrathin Oxides/Gate Stacks B. Govoreanu (1,2), P. Blomme (1,2), K. Henson (1), J. Van Houdt (1), K. De Meyer (1,2); 1) IMEC, SPDT Division, Leuven, Belgium; 2) K.U. Leuven, Electrical Engineering Dept., Leuven, Belgium
15.20 – 15.40	Performance Evaluation of Ultrathin Gate-oxide CMOS Circuits A. Marras, I. De Munari, D. Vescovi, P. Ciampolini; Dip. Di Ing. Dell’Informazione, Università di Parma, Parma, Italy
15.40 – 16.00	Coffee Break and Poster session
16.00 – 16.20	On the Extraction of the Channel Current in Permeable Gate Oxide MOSFETs P. Palestri (1), D. Esseni (1), L. Selmi (1), G. Guegan (2), E. Sangiorgi (1); 1) DIEGM, University of Udine, Udine, Italy; 2) CEA-LETI, Grenoble, France
16.20 – 16.40	Channel Debiasing and Gate Current Modelling in Advanced CMOS Devices F. Gilibert (1), D. Rideau (1), S. Bernardini (2), P. Scheer (1), M. Minondo (1), D. Roy (1), G. Gouget (1), A. Juge (1); ST-Microelectronics, Crolles, France; 2) L2MP UMR CNRS, Université de Provence, Marseille, France
	FRIDAY MORNING, March 21, 2003 – PALAZZO ANTONINI
9.00	Session 2.1: Device Reliability and Noise Chairpersons: F. Balestra (LPCS/IMEP, IMP Grenoble/CNRS, France) and L. Risch (Infineon Technologies, Munich, Germany)
9.00 – 9.40	Invited paper: Challenges and Opportunities of Ultrathin Channel Single- and Multiple-gate MOSFET’s M. Ieong (1,3), J. Kedzierski (3), Z. Ren (1), B. Doris (1), E. Nowak (2); IBM (SRDC) 1) Microelectronic Division, Hopewell Junction, NY, USA; 2) Microelectronic Division, Essex Junction, VT, USA; 3) T.J. Watson Research Center, Yorktown Height, NY, USA
9.40 – 10.00	Analysis of Mechanical Stress Effects in Short Channel MOSFETs C. Gallon (1), G. Reimbold (1), G. Ghibaudo (2), A. Bianchi (3), R. Gwoziecki (1,3); 1) CEA-DRT-Leti, Grenoble, France; 2) IMEP, Grenoble, France; 3) ST-Microelectronics, Crolles, France
10.00 – 10.20	Comparative Analysis of the RF and Noise Performance of Bulk and Single-Gate Ultra-thin SOI MOSFETs by Numerical Simulation M. Alessandrini, S. Eminente, S. Spedo, C. Fiegna; Department of Engineering, University of Ferrara, Ferrara, Italy
10.20 – 10.40	Direct gate tunneling related excess noise in ultra-thin gate oxide Partially Depleted SOI MOSFETs F. Dieudonné (1), O. Rozeau (2), J. Jomaah (1), F. Balestra (1); 1) IMEP/ENSERG, Grenoble, France; 2) CEA/LETI, Grenoble, France
10.40 – 11.00	Coffee Break and Poster session
11.00 – 11.20	Influence of ultra-thin gate oxide on the electric performance and low frequency noise of sub -0.1μm NMOSFETs M. Fadlallah (1,3), G. Ghibaudo (1), J. Jomaah (1), G. Guégan (2); 1) IMEP/LPCS, ENSERG, Grenoble, France; 2) CEA/LETI, Grenoble, France; 3) LAM UFR Sciences, Reims, France
11.20 – 11.40	Reliability of ZrO2 films grown by atomic layer deposition D. Caputo (1), F. Irrera (1), S. Salerno (1), S. Spiga (2), M. Fanciulli (2); 1) Dept. Electronic Eng., Univ. “La Sapienza”, Roma, Italy; Laboratorio MDM-INFM, Agrate Brianza, Italy
11.40 – 12.00	Evolution of Si-SiO2 interface trap density under electrical stress in MOSFETs with ultrathin oxides F. Rahmoune, D. Bauza; IMEP, UMR CNRS 5130, INPG, ENSERG, Grenoble, France
12.00 – 12.20	Study of a single dangling bond (Pb0 center) at the SiO2/Si interface in deep submicron MOS transistors L. Militaru, A. Souifi; LPM, INSA de LYON, Villeurbanne, France
	FRIDAY AFTERNOON, March 21, 2003 – PALAZZO ANTONINI
14.20	Session 2.2: Advanced transport models Chairpersons: E. Sangiorgi (DEIS, University of Bologna, Italy) and H. Iwai (Tokyo Institute of Technology, Tokyo, Japan)
14.20 – 15.00	Invited paper: Simulation at the Scaling Limit M. Lundstrom, Purdue University, IN, USA
15.00 – 15.20	Rigorous Modeling of Mobilities and Relaxation Times Using Six Moments of the Distribution Function T. Grasser, H. Kosina, S. Selberherr; Institute for Microelectronics, TU Vienna, Vienna, Austria
15.20 – 15.40	Development of an analytical mobility model for the simulation of ultra thin SOI MOSFETs M. Alessandrini (1), D. Esseni (2), C. Fiegna (1); 1) Department of Engineering, University of Ferrara, Ferrara, Italy; 2) DIEGM, University of Udine, Udine, Italy
15.40 – 16.00	Coffee Break and Poster session
16.00 – 16.20	Modeling End-of-The-Roadmap CMOS devices G. Curatola, G. Fiori, G. Iannaccone; Dipartimento di Ingegneria dell’Informazione, Università degli studi di Pisa, Pisa, Italy
16.20 – 16.40	Theoretical investigation of hole transport in strained silicon inversion layer F. Payet, N. Cavassilas, J.L. Autran; Laboratoire Matériaux et Microélectronique de Provence (L2MP, UMR CNRS 6137) Bâtiment IRPHE, Marseille, France
16.40 – 17.00	Quantum transport simulation in DG MOSFETs using a tight binding Green’s function formalism M. Bescond (1), J.L. Autran (2), M. Lanoo (1); 1) Laboratoire Matériaux et Microélectronique de Provence, Maison des Technologies, Toulon, France ; 2) Bâtiment IRPHE, Marseille, France
17.00 – 17.20	Full-band approaches to the electronic properties of nanometer-scale MOS structures F. Sacconi (1), M. Povolotskyi (1), A. Di Carlo (1), P. Lugli (1), M. Städele (2); 1) INFM-Dept. Electronic. Eng., University of Rome “Tor Vergata”, Rome, Italy; 2) Infineon Technologies AG, Corporate Resarch, Munich, Germany

 

	Session P: Poster Session
P.1	Consistent Comparison of Tunneling Models for Device Simulation A. Gehring, H. Kosina, T. Grasser, S. Selberherr; Institute for Microelectronics, TU Vienna, Vienna, Austria
P.2	Double gate MOSFET with vertical channel J. Moers, St. Trellenkamp, M. Goryll, S. Hogg, P. Kluth, Q.-T. Zhao, A. v.d. Hart, M. Marso, S. Mantl, P. Kordoš, H. Lüth; Institute of Thin Films and Interfaces Research Centre Jülich, Jülich, Germany
P.3	The vertical Tunnel FET Inventer Th. Nirschl (1), S. Sedlmaier (2), P.-F. Wang (1), W. Hansch (1), I. Eisele (2), D. Schmitt-Landsiedel (1); 1) Technical University Münich, Institute of Technical Electronics, Münich, Germany; 2) University of the Bundeswehr Münich, Institute of Physics, Neubiberg, Germany
P.4	A predictive nano-crystal Flash memory simulator S. Bernardini (1), R. Laffont (1), P. Masson (1), G. Ghibaudo (2), S. Lombardo (3), B. De Salvo (4), C. Gerardi (5); 1) L2MP, UMR CNRS 6137, Marseille, France; 2) IMEP, ENSERG, BP 257, Grenoble, France; 3) CNR-IMM, Catania, Italy; 4) CEA/LETI, BP 85X, Grenoble, France; 5) ST-Microelectronics, Catania, Italy
P.5	Theoretical Modeling of the Double Gate MOS Resonant Tunneling Diode B. Majkusiak; Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Warsaw, Poland
P.6	Temperature Effects in sub 50 nm CMOS Circuits S. Schwantes, W. Krautschneider; Technical University of Hamburg, Hamburg, Germany