Dipartimento di Ingegneria Elettrica, Gestionale e Meccanica
Site: via delle Scienze, 208 - 33100 Udine - Italy
Administrative Secretary's Office: +39 0432 558251 (fax)

 

Confirmed Invited Speakers

1. M. Ashraful Alam, Bell Laboratories - Lucent Tech.
	"A Computational Study of Oxide Breakdown - Theory and Experiments"
2. Ilan Bloom, Saifun
	"NROM - a New Non Volatile Memory Technology: from Device to Products"
3. Andrea Ghetti, ST Microelectronics
	"Characterization and Modeling of the Tunneling Current in Si/SiO2/Si Structures with Ultra-thin Oxide Layer"
4. Giovanni Campardo , STMicroelectronics
	"Architecture of Non Volatile Memory with Multi-bit cells"
5. Evgeni Gusev, IBM
	"Ultrathin High-k Metal Oxides on Silicon: Processing, Characterization and Integration Issues"
6. Marc Heyns, IMEC
	"High-k Dielectric Materials Prepared by Atomic Layer CVD"
7. Hiroyuki Kageshima, NTT
	"Theory of Si thermal oxide growth rate taking account of interfacial Si emission effects"
8. Di-Son Kuo, TSM Corp. - Taiwan
	"An Embedded Flash Technolgy Using Split-gate Cell"
9. Salvatore Lombardo, CNR - IMETEM
	"Intrinsic Dielectric Breakdown of Ultra-thin Gate Oxide"
10. Lalita Manchanda, Bell Laboratories - Lucent Tech.
	"Multicomponent High-k Gate Dielectric for the Silicon Industry"
11. Marco Mastrapasqua, Bell Laboratories - Lucent Tech.
	"Low-field Transport in Ultra-thin SOI Structures"
12. Yukinori Ono, NTT
	"Single-electron and Quantum SOI Devices"
13. Shinichi Takagi, Toshiba Corporation
	"Carrier transport properties of thin gate oxides after soft and hard breakdown"
14. Hidemi Takasu, Rohm
	"Ferroelectric Memories and their Applications"
15. Olivièr Vancauwenberghe, ESIEE - Paris
	"Microsensors and MEMS Integrated on SOI"
16. Eric M. Vogel, National Institute of Standards and Technology
	"Reliability of Ultra-thin Silicon-dioxide under Substrate Hot-electron, Substrate Hot-hole, and Tunneling Stress"
17. René Zingg, Philips
	"High-voltage Devices on SOI"